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[VHDL-FPGA-Verilog] pinlvji 频率计VHDL编程

Description: 频率计VHDL编程。设计一个4位数字显示的十进制频率计，其测量范围为1MHz，测量值通过4个数码管显示以8421BCD码形式输出，可通过开关实现量程控制，量程分10kHz、100kHz、1MHz三档(最大读数分别为9.999kHz、99.99kHz、999.9kHz)； 当输入信号的频率大于相应量程时，有溢出显示。 -Cymometer VHDL programming. Design of a 4-digit decimal display frequency, the measurement range of 1MHz, the measured value through the four LED 8421BCD code shows the form of output can be controlled through the switch range, range at 10kHz, 100kHz, 1MHz Three (maximum reading were 9.999kHz, 99.99kHz, 999.9kHz) when the input signal is greater than the corresponding frequency range, it shows overflow.
Platform: | Size: 90168 | Author: testsb | Hits:

[VHDL-FPGA-Verilog] 数字频率计实验报告

Description: 课程设计要求设计并用FPGA实现一个数字频率计，具体设计要求如下： 测量频率范围： 10Hz～100KHz 精度： ΔF / F ≤ ±2 % 系统外部时钟： 1024Hz 测量波形： 方波 Vp-p ＝ 3～5 V 硬件设备：Altera Flex10K10 五位数码管 LED发光二极管 编程语言：Verilog HDL / VHDL-curriculum design and FPGA design to achieve a digital frequency meter, the specific design requirements are as follows : measurement frequency range : 10Hz to 100KHz precision : F/F 2% external clock system : 1024Hz Waveform Measurement : square Vp-p = 3 ~ 5 V hardware : Altera Flex10K10 five digital LED light emitting diode programming languages : Verilog HDL/VHDL
Platform: | Size: 144384 | Author: 兰 | Hits:

[VHDL-FPGA-Verilog] 一些译码器源代码

Description: 内有LED译码器，汉明纠错译码器，地址译码器，最高优先译码器，双2－4译码器等VHDL的源代码-decoder, Hamming error correction decoder, address decoder, the highest priority decoder, dual 2-4 decoder such as VHDL source code
Platform: | Size: 4096 | Author: 蔡孟颖 | Hits:

[VHDL-FPGA-Verilog] 流水灯VHDL程序

Description:
Platform: | Size: 1024 | Author: 韦元龙 | Hits:

[VHDL-FPGA-Verilog] 7led

Description: 7段发光二极管vhdl程序，可以验证led的fpga验证程序-seven of the light-emitting diode VHDL procedures can verify they simply led to the certification process
Platform: | Size: 282624 | Author: 马永涛 | Hits:

[VHDL-FPGA-Verilog] 08787743vhdl

Description: 用VHDL语言编写的LED显示器驱动电路的设计源程序-using VHDL prepared by the LED display driver circuit design source
Platform: | Size: 3072 | Author: 冯 | Hits:

[VHDL-FPGA-Verilog] ledleft

Description: xilinx的SPARTAN-3E入门开发板实例 根据官方公布的led移动范例改写。 原范例仅提供了源代码、烧写文件以及dos窗口下使用的烧写bat文件。 本实例采用了ise7.1i创建，在ise下重建整个工程，有助于初学者理解使用。-xilinx the SPARTAN-3E portal development board examples According to the official announcement led to the mobile Examples rewritten. Original examples provided only source code, dos burning documents and the use of the window of burning bat documents. The examples used ise7.1i creation, the redevelopment of the entire ise project will help beginners understand the use.
Platform: | Size: 393216 | Author: 韩兆伟 | Hits:

[File Format] VHDL_clock

Description: 用VHDL能进行正常的时、分、秒计时功能、分别有6个数码管显示24小时、60分钟、60秒钟的计数器显示。-VHDL can be used for normal hours, minutes and seconds timing were six LED display 24 hours 60 minutes, 60 seconds showed that the counter.
Platform: | Size: 105472 | Author: lianbin | Hits:

[assembly language] C51CrossLight

Description: 1.设计一个交通灯控制器。 2.利用学习机上的发光二极管，设定东、南、西、北4个方向，各3个灯（红、黄、绿）。交通灯控制器正常工作时，南北方向红灯亮3秒，黄灯闪2秒，绿灯亮3秒，以此类推。东西方向绿灯亮3秒，黄灯闪2秒，红灯亮3秒，以此类推。 3.设定两个紧急按钮，一个控制南北灯，一个控制东西灯。当按下相应的紧急键时，其控制方向的交通灯亮绿灯，其他方向的交通灯亮红灯，至自控键松开，恢复正常交通控制。 -1. Design of a traffic light controller. 2. Use of learning machine on the LED and set the East, South, West, North 4 direction, the three lights (red, yellow, green). Traffic signal controller normal working hours, the north- and south-bound red light three seconds, two seconds flashing yellow light, green light-three seconds, and so on. East-west direction green three seconds, two seconds flashing yellow light, red light three seconds, and so on. 3. Set two emergency buttons, a north-south control lights, a light control things. When pressing the corresponding key emergency, its control the traffic lights green, the other direction, the traffic lights class. Key to loose control and restore normal traffic control.
Platform: | Size: 10240 | Author: wangpeng | Hits:

[File Format] FPGA_27eg

Description: FPGA很有价值的27实例.rar 包括 LED控制VHDL程序与仿真 2004.8修改.doc； LED控制VHDL程序与仿真； LCD控制VHDL程序与仿真 2004.8修改； LCD控制VHDL程序与仿真； ADC0809 VHDL控制程序； TLC5510 VHDL控制程序； DAC0832 接口电路程序； TLC7524接口电路程序； URAT VHDL程序与仿真； ASK调制与解调VHDL程序及仿真； FSK调制与解调VHDL程序及仿真； PSK调制与解调VHDL程序及仿真； MASK调制VHDL程序及仿真； MFSK调制VHDL程序及仿真； MPSK调制与解调VHDL程序与仿真； 基带码发生器程序设计与仿真； 频率计程序设计与仿真； 采用等精度测频原理的频率计程序与仿真； 电子琴程序设计与仿真 2004.8修改； 电子琴程序设计与仿真； 电梯控制器程序设计与仿真； 电子时钟VHDL程序与仿真； 自动售货机VHDL程序与仿真； 出租车计价器VHDL程序与仿真 2004.8修改； 出租车计价器VHDL程序与仿真； 波形发生程序； 步进电机定位控制系统VHDL程序与仿-FPGA value of the 27 examples. Rar including LED control procedures and VHDL simulation 200 4.8 amendments. doc; LED control procedures and VHDL simulation; LCD control procedures and VHDL simulation 2004.8 modified; LCD control procedures and VHDL simulation; Connection between ADC 0809 VHDL control procedures; TLC5510 VHDL control procedures; DAC0832 interface circuits; TLC7524 interface circuits; URAT procedures and VHDL simulation; ASK modulation and demodulation process and VHDL simulation; FSK modulation and demodulation process and VHDL simulation; PSK modulation and demodulation process and VHDL simulation; MASK modulation procedures and VHDL simulation; MFSK modulation procedures and VHDL simulation; MPSK modulation and demodulation process and VHDL simulation; Base-band code gene
Platform: | Size: 1278976 | Author: 高 | Hits:

[Communication] vc++toled

Description: 本人用在公司点阵条屏通讯送点阵数据的上位几软件,有两点可以参考 1.里面的点阵获取没有采用字库,而是自己从屏幕获取.可以发送WINDOWS有的任意可以写出来的字体. 2.实现了串口的发送.-I used the company lattice screen data communications sent to the upper lattice several software two of which may be a reference. there is no access to the lattice using font, but their access to the screens. Windows can send some arbitrary able to write the characters. 2. achieved a string Send the mouth.
Platform: | Size: 48128 | Author: zxf | Hits:

[VHDL-FPGA-Verilog] vhdl_traffic

Description: 模拟交通灯实验 模拟路口的红黄绿交通灯的变化过程，用LED 灯表示交通灯，并在数码管上显示当 前状态剩余时间。-simulation experiment simulated traffic lights junction of red, yellow, and green traffic lights to the process of change, said LED lights for traffic lights, and the digital tube display the current state of the remaining time.
Platform: | Size: 199680 | Author: 赵海东 | Hits:

[VHDL-FPGA-Verilog] LED_clock_quartus

Description: 用VHDL语言实现数显时钟，devid200.vhd为分频模块，scan.vhd为LED扫描模块，timecount.vhd为计数模块-VHDL digital clock, devid200.vhd for frequency module, scan.vhd for LED scanning module, timecount.vhd for counting module
Platform: | Size: 3072 | Author: 王龙 | Hits:

[Other] vhdl

Description: 基于MAXPLUS II 的软件设计，这里面有几个小程序，用于VHDL的GDF设计，含有LED数码管的显示驱动程序，还有3选一，十选一程序。-II FPGA-based design software, there are several small procedures, GDF for VHDL design with a digital LED display driver of the procedures, there is a three elections. 10 election procedure.
Platform: | Size: 2048 | Author: 梁兵 | Hits:

[VHDL-FPGA-Verilog] traffic

Description: xilinx完成一个模拟的十字路口交通信号灯，主干道上的绿灯时间为30s，支干道的绿灯时间为30s，且交通灯从绿变红时，有6s黄灯亮的时间间隔。当然每种状态的倒计时的时间值应显示到LED数码管上。-Xilinx completed in a simulated traffic lights at a crossroads, a main road on the green time for the 30s, branch roads green time for 30s, and red traffic lights from green when 6s yellow light time interval. Of course, each state s countdown time value should be shown on the LED digital tube.
Platform: | Size: 95232 | Author: haolj | Hits:

[VHDL-FPGA-Verilog] SCAN8_DIG

Description: 8点阵列LED显示屏的 VHDL扫描程序-8:00 Array LED display VHDL scanner
Platform: | Size: 1024 | Author: ww | Hits:

[Linux-Unix] qiduan

Description: 七段数码管显示程序，用VHDL语言编译的-Seven-Segment LED display program, compiled using VHDL language
Platform: | Size: 433152 | Author: 史乐 | Hits:

[VHDL-FPGA-Verilog] vhdl3

Description: 时序电路——抢答器，K1、K2、K3、K4各控制一个按钮，DJ代表主持人，在抢答开始前，DJ先按一下按钮，然后在开始比赛，K1—K4中任意按下按钮后，其他钮按下均无效，重新比赛时，DJ需要再按一下按钮。抢答结果用LED显示。-Sequential Circuits- Answer devices, K1, K2, K3, K4 the control of a button, DJ on behalf of the host before the start of the Answer, DJ press the button, and then at the beginning of competition, K1-K4 in the arbitrary press the button and press the other buttons are invalid, re-match, DJ need to then click the button. Answer the result of using LED display.
Platform: | Size: 97280 | Author: wang | Hits:

[VHDL-FPGA-Verilog] led_vhdl

Description: LCD点阵阵控制,可输出不同的图形和位置.可随意调整显示格式.-LCD bursts of control points can be output in different graphics and location. Can easily adjust display format.
Platform: | Size: 2048 | Author: 王晶 | Hits:

[SCM] dmc_verilog

Description: 本示例中使用了一个DCM模块，将输入时钟50MHz，倍频到100MHz，分频到25MHz，不同的频率值通过LED进行演示。-This example uses a DCM module, the input clock 50MHz, frequency-doubled to 100MHz, frequency to 25MHz, the frequency of different values demonstrated through the LED.
Platform: | Size: 631808 | Author: 沈天平 | Hits:
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